Radio Frequency (RF) & Wireless Design

In late 2017 Xilinx quietly introduced a new form of Zync System on Chip (SoC) which is the next generation of Software Defined Radios (SDR) in their RF-SoC product line :

https://www.xilinx.com/products/silicon-devices/soc/rfsoc.html

This was included in their latest offerings of Ultrascale+ Logic FPGAs line and since then there have been 3 generations of the RF-SoC Ultrascale+ Zync. Not only does the Zync SoC offer an ARM quad core A53 64-bit CPU, but it also offers a dual core ARM Cortex R5 coprocessor to handle subtasks related to the FPGA and off load CPU housekeeping.

The key to this SoC is that it offers integration of the historically external multi-giga sampling rate ADCs for receiving (decimation) and multi-giga sampling rate DACs for transmitting (interpolation). There is also a Soft-Decision Forward Error Correction (SD-FEC) mechanism for ensuring data recovering as a state machine to (again) off load CPU overhead.

These state-of-the-art SoC FPGAs will bring forth a new generation of SDR as well as for 5G applications of phased arrays, RADAR, test equipment, and satellite communications. The latest generation will go up to 6 GHz for single Hertz resolution, but I expect this to double (to 12 GHz) or possibly triple to (18 GHz) within the next decade.

Although not state of the art in bit level ADCs  as 14-b, I also expect these to go to at least 16b and likely to 18b with a decade as well.

So behold a new era in SDR and RF digital communications is emerging for the next generation of RF technology !